Stone Pillar SuiteTM – DesignRuleBuilder
Automated Layout Design Rule & DRC Run Set Generation --
Stone Pillar Suite - DesignRuleBuilder enables rapid, automated
calculation, generation and documentation of layout design rules. Complete DRC
/ LVS run sets for a variety of DRC tools can be generated automatically from
these rules. Rules intelligently incorporate information on unit process
manufacturing capabilities (such as inter-layer alignment tolerances and unit
process variations) and electrical constraints. Maximize yield by automatically
including process variability factors in layout design rule values. Easily
regenerate complete DRC / LVS run sets as unit process capabilities or
electrical constraints change. Change effortlessly from one DRC / LVS tool to
another. Supported DRC / LVS tools include:
DesignRuleBuilder also creates complete, searchable, filterable documentation
including revision tracking for generated design rules.
Features & Benefits
- Generate optimal layout design rules based on unit process
capability
- Automate DRC run set generation and flexibly create run sets for
a variety of DRC tools at the push of a button
- Optimize yield by accounting for statistical process variances
in layout design rules
- Calculate and rank the impact of unit process SPC improvement
opportunities to layout design rules
- Automatically generates layout design rule documentation and
manages document revisions
- Filter and search inputs and generated rules by device type,
layer, and rule type
- Automatically generate readable layout design rule and DRC
run set documentation
- Multi - stage line width bias and variance compilation
- Automatically propagate rules and changes to Stone Pillar Suite
Parameterized Layout Module for immediate test chip updates
- Avoid missing, incorrect, or redundant layout design rules
- 1, 3 and 6 sigma design rule variance analysis
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Screen Images
| Users select from available rule types in order to
determine the rules they will generate.
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| The LDR tool supports registration to any underlying layer
or to the wafer and reflects the resulting misalignment variance
in the generated rules.
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| Generated rules can be filtered by device, layer, or type
and form the basis for automatic document generation.
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"Cadence" and "DRACULA" are registered trademarks of Cadence Design Systems, Inc.
"Calibre" is a registered trademark of Mentor Graphics Corporation.
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